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X-WR-CALDESC:Events for UW QuantumX
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DTSTART;TZID=America/Los_Angeles:20260213T133000
DTEND;TZID=America/Los_Angeles:20260213T143000
DTSTAMP:20260427T220851
CREATED:20251230T224908Z
LAST-MODIFIED:20260407T182043Z
UID:8273-1770989400-1770993000@www.quantumx.washington.edu
SUMMARY:Michael Beverland (IBM)\, QISE Seminar: Real-time decoding for fault-tolerant quantum computers
DESCRIPTION:Abstract: Fault-tolerant quantum computers involve running circuits on quantum hardware that sometimes undergo faults in such a way that the faults can be identified and fixed to ensure the quantum computation runs reliably. To do this\, information is protected in a quantum error correcting code\, and carefully-designed logical operations are carried out on the protected information\, with information about the noise that arises during the entire process being generated in a continuous stream of classical output called the syndrome. Decoding is the task of taking the syndrome data and using it to identify what faults occurred so that they can be fixed. This decoding task is run on a classical computer\, and is needed to make the quantum computer work – but it is a very challenging unsolved problem to design a decoding algorithm that performs well enough in practice.Real-time decoding for fault tolerance is a central challenge as we move beyond NISQ. The decoding timescale is set by the QEC cycle time of the hardware\, which is microseconds for superconducting platforms. Meeting this constraint likely requires specialized classical hardware such as FPGAs or ASICs\, whose high degree of parallelism changes the relative performance of decoding algorithms\, for example allowing Gaussian elimination to run in linear parallel time on FPGAs rather than cubic time on CPUs\, and therefore motivates hardware-aware redesign rather than direct porting of CPU-based methods.In this talk\, I discuss recent progress toward real-time decoding under these constraints\, and argue that message-passing decoders\, particularly the Relay-BP algorithm\, offer a promising route to real-time decoding. Relay-BP improves on the convergence of standard belief propagation while retaining a lightweight\, highly parallel structure suitable for FPGA implementation\, and significantly outperforms alternative decoders for quantum LDPC codes.Beyond average decoding speed\, I address the backlog problem that arises from variable decoding latency. I present conditions on decoder latency distributions under which fast average-case decoding and sufficiently light latency tails allow decoding to keep pace with syndrome generation\, ensuring bounded computational slowdown in large-scale fault-tolerant computations. \n\n\n\n \n\n\n\nLinkedIn: Michael Beverland
URL:https://www.quantumx.washington.edu/calendar/michael-beverland-ibm/
LOCATION:Electrical and Computer Engineering (ECE)\, Room 037\, 185 W Stevens Wy NE\, Seattke\, Washington\, 98185
CATEGORIES:Electrical & Computer Engineering
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DTSTART;TZID=America/Los_Angeles:20260220T133000
DTEND;TZID=America/Los_Angeles:20260220T143000
DTSTAMP:20260427T220851
CREATED:20251230T225057Z
LAST-MODIFIED:20260407T182625Z
UID:8275-1771594200-1771597800@www.quantumx.washington.edu
SUMMARY:Daniel Higginbottom (Simon Fraser University)\, QISE Seminar: Engineering silicon colour centres for quantum networks
DESCRIPTION:Abstract \n\n\n\nThe performance of quantum networks for long-distance communication\, sensing\, and distributed quantum computing will be contingent upon the quality of their light-matter interconnects. For networks at scale\, these interconnects should be manufacturable and deployable. Solid-state colour centres are single-photon emitters which may offer optically-coupled spin qubit registers for deployable entanglement distribution networks. Of the potential semiconductor hosts\, silicon is an ideal platform for commercial quantum technologies. It is a “semiconductor vacuum” with record-setting spin qubit performance\, and silicon nanofabrication is an advanced industrial process and the backbone of the microelectronics industry. Although they were neglected until quite recently\, silicon colour centres are now established as a quantum platform with technological appeal: they emit in or near the optical telecommunications bands\, host intrinsic spin qubit registers\, and integrate directly with photonic and electronic circuits on chip. In this talk I will discuss progress towards networked silicon colour centre devices and identify emerging candidates from the rapidly expanding alphabet of silicon colour centres. In particular\, I will summarize recent results with the T centre\, a CCH defect in silicon. A surprising isotope-dependent lifetime effect suggests that the T centre can be made almost perfectly efficient by isotopic substitution. Cavity-integrated T centres show dramatic Purcell enhancements\, enabling faster and more coherent emission\, and indistinguishable emission is employed to entangle T centres on separate chips\, six meters apart. Determining the hyperfine tensors of the T centre’s intrinsic spin qubits reveals unusual schemes for protecting spin coherence during entanglement attempts. Finally\, a new class of opto-electronic devices combining single emitters\, optical resonators\, and diodes enable a host of spin-photon control techniques including electrically-injected single-photon emission\, Stark tuning\, and electrical spin initialization. These results illustrate how silicon colour centres may be deployed as an on-chip spin-photon quantum processor\, and how these processors may be connected over optical fibre in a metropolitan-scale quantum internet.Bio  \n\n\n\nDr Daniel Higginbottom is an Assistant Professor in the Simon Fraser University Department of Physics and a Director at the quantum technology company Photonic Inc. His research has spanned quantum information with platforms including integrated photonics\, optically trapped atoms\, electrically trapped ions\, and silicon spin qubits\, for which he received a Banting Research Fellowship. His achievements include benchmark results with single photon sources and optical quantum memories. Recently\, he has pioneered the device integration of silicon colour centres\, most notably the T centre\, for quantum technologies. The primary goal of his research is developing practical\, and scalable\, quantum technology platforms.
URL:https://www.quantumx.washington.edu/calendar/daniel-higginbottom-simon-fraser-university/
LOCATION:Electrical and Computer Engineering (ECE)\, Room 037\, 185 W Stevens Wy NE\, Seattke\, Washington\, 98185
CATEGORIES:Electrical & Computer Engineering
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DTSTART;TZID=America/Los_Angeles:20260226T103000
DTEND;TZID=America/Los_Angeles:20260226T113000
DTSTAMP:20260427T220851
CREATED:20260226T201913Z
LAST-MODIFIED:20260226T201914Z
UID:9044-1772101800-1772105400@www.quantumx.washington.edu
SUMMARY:UW ECE Research Colloquium Lecture Series: Yanjie Shao\, Massachusetts Institute of Technology
DESCRIPTION:Campus location: Electrical and Computer Engineering Building (ECE)Campus room: ECE 037Accessibility Contact: events@ece.uw.edu \nEvent Link \nUltra-Scaled Energy-Efficient Electronics \nAbstract  \nThe explosive growth of data-centric computing in the era of artificial intelligence has made energy efficiency a central challenge for modern microelectronics. Two fundamental limitations now dominate: (1) the “power wall”\, where stalled voltage scaling in advanced complementary metal–oxide–semiconductor (CMOS) technologies has largely limited further reductions in transistor switching energy\, and (2) the “memory wall”\, where data movement between computing and memory units increasingly dominates energy cost and restricts information throughput. In this talk\, I will present two complementary approaches\, leveraging new material systems and nanoscale processing to enable unprecedented device operating regimes and scalable 3D integration paradigms beyond conventional CMOS scaling. First\, I target a supply voltage ≤ 0.3 V by exploiting quantum-mechanical tunneling in a broken-band heterojunction semiconductor system (GaSb/InAs). I will show that a combination of sub-thermionic turn-on\, high drive current and ultimate device scalability can be achieved simultaneously in a vertical-nanowire tunneling transistor configuration. Second\, I will describe a low-thermal-budget (≤ 400 °C) electronic technology integration platform enabled by amorphous oxide semiconductors (AOS) and ferroelectric (FE) hafnium-zirconium oxide. By exploiting plasma-enhanced atomic-layer deposition\, enhancement-mode AOS transistors with record logic performance are realized\, and nanoscale FE memory transistors comprising a single domain are demonstrated. Together\, these results highlight how emerging materials can drivehigh-performance and multifunctional devices that unlock new pathways for future energy-efficient 3D electronics. \nBiography  \nYanjie Shao is currently a postdoctoral researcher at the Massachusetts Institute of Technology (MIT) in the Microsystems Technology Laboratories (MTL)\, working with Prof. Jesús del Alamo and Prof. Dimitri Antoniadis. He received his Ph.D. (2023) and S.M. (2021) in Electrical Engineering from MIT\, advised by Prof. Jesús del Alamo\, and his B.S. in Physics from the University of Science and Technology of China (USTC). His research focuses on addressing fundamental materials\, device\, and integration challenges to advance energy-efficient semiconductor and microelectronics technologies. He is a recipient of the 2023 Intel Outstanding Researcher Award.
URL:https://www.quantumx.washington.edu/calendar/uw-ece-research-colloquium-lecture-series-yanjie-shao-massachusetts-institute-of-technology/
LOCATION:Electrical and Computer Engineering (ECE)\, Room 037\, 185 W Stevens Wy NE\, Seattke\, Washington\, 98185
CATEGORIES:Electrical & Computer Engineering
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