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DTSTART;TZID=America/Los_Angeles:20260226T103000
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UID:9044-1772101800-1772105400@www.quantumx.washington.edu
SUMMARY:UW ECE Research Colloquium Lecture Series: Yanjie Shao\, Massachusetts Institute of Technology
DESCRIPTION:Campus location: Electrical and Computer Engineering Building (ECE)Campus room: ECE 037Accessibility Contact: events@ece.uw.edu \nEvent Link \nUltra-Scaled Energy-Efficient Electronics \nAbstract  \nThe explosive growth of data-centric computing in the era of artificial intelligence has made energy efficiency a central challenge for modern microelectronics. Two fundamental limitations now dominate: (1) the “power wall”\, where stalled voltage scaling in advanced complementary metal–oxide–semiconductor (CMOS) technologies has largely limited further reductions in transistor switching energy\, and (2) the “memory wall”\, where data movement between computing and memory units increasingly dominates energy cost and restricts information throughput. In this talk\, I will present two complementary approaches\, leveraging new material systems and nanoscale processing to enable unprecedented device operating regimes and scalable 3D integration paradigms beyond conventional CMOS scaling. First\, I target a supply voltage ≤ 0.3 V by exploiting quantum-mechanical tunneling in a broken-band heterojunction semiconductor system (GaSb/InAs). I will show that a combination of sub-thermionic turn-on\, high drive current and ultimate device scalability can be achieved simultaneously in a vertical-nanowire tunneling transistor configuration. Second\, I will describe a low-thermal-budget (≤ 400 °C) electronic technology integration platform enabled by amorphous oxide semiconductors (AOS) and ferroelectric (FE) hafnium-zirconium oxide. By exploiting plasma-enhanced atomic-layer deposition\, enhancement-mode AOS transistors with record logic performance are realized\, and nanoscale FE memory transistors comprising a single domain are demonstrated. Together\, these results highlight how emerging materials can drivehigh-performance and multifunctional devices that unlock new pathways for future energy-efficient 3D electronics. \nBiography  \nYanjie Shao is currently a postdoctoral researcher at the Massachusetts Institute of Technology (MIT) in the Microsystems Technology Laboratories (MTL)\, working with Prof. Jesús del Alamo and Prof. Dimitri Antoniadis. He received his Ph.D. (2023) and S.M. (2021) in Electrical Engineering from MIT\, advised by Prof. Jesús del Alamo\, and his B.S. in Physics from the University of Science and Technology of China (USTC). His research focuses on addressing fundamental materials\, device\, and integration challenges to advance energy-efficient semiconductor and microelectronics technologies. He is a recipient of the 2023 Intel Outstanding Researcher Award.
URL:https://www.quantumx.washington.edu/calendar/uw-ece-research-colloquium-lecture-series-yanjie-shao-massachusetts-institute-of-technology/
LOCATION:Electrical and Computer Engineering (ECE)\, Room 037\, 185 W Stevens Wy NE\, Seattke\, Washington\, 98185
CATEGORIES:Electrical & Computer Engineering
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DTSTART;TZID=America/Los_Angeles:20260305T103000
DTEND;TZID=America/Los_Angeles:20260305T113000
DTSTAMP:20260428T015515
CREATED:20260226T202059Z
LAST-MODIFIED:20260304T213030Z
UID:9045-1772706600-1772710200@www.quantumx.washington.edu
SUMMARY:UW ECE Research Colloquium Lecture Series: Shuhan Liu\, Stanford University
DESCRIPTION:Event interval: Single day eventCampus location: Electrical and Computer Engineering Building (ECE)Campus room: ECE 037Accessibility Contact: events@ece.uw.eduEvent Types: Lectures/SeminarsLink: https://www.ece.uw.edu/colloquia/middas-memory-integration-and-data-dis-aggregation/ \nMIDDAS: Memory Integration and Data Dis-Aggregation \nAbstract \nSince the invention of the integrated circuit in 1958\, the integration of exponentially more devices onto a single chip has transformed    computing—yet memory remains largely separated from logic\, resulting in a “memory wall”. Recent advances in memory research have introduced a variety of new memory technologies. My research focus\, Memory Integration and Data Dis-Aggregation (MIDDAS)\, envisions a future where massive\, diverse memories are physically integrated yet functionally store disaggregated data. MIDDAS encompasses a continuous spectrum of memory characteristics. This is exemplified by BRIDGE (Blended Retention-Indexed Diverse Gain cEll)\, a gain cell memory platform developed in my PhD research. The 2-transistor (2T) gain cell memory offers high density and CMOS integration compatibility. By introducing oxide semiconductor (OS) transistors with ultra-low leakage current (< 1e-17 A/μm)\, BRIDGE expands the design space to support retention times spanning microseconds to seconds. BRIDGE is demonstrated on fabricated N40 CMOS+X monolithic 3D integration chip with Atomic-Layer-Deposited (ALD) Indium Tin Oxide (ITO) FET. Hybrid gain cell (OS-Si) demonstrates 3x density and lower energy compared to high-density (HD) SRAM\, scalable to N5 and beyond. Furthermore\, integrating gain cells with non-volatile memories (e.g.\, RRAM) unlocks synergistic system-level benefits from device-circuit-architecture co-design\, embodying the “1+1>2” philosophy where diverse memory technologies collaboratively enhance system functionality through integration. MIDDAS repositions memory as a scalable\, intelligent toolbox for AI-era computing\, capitalizing on the predictability of memory access\, bridging device innovation with software demands. \nBiography \nShuhan Liu is a PhD candidate at Stanford University\, advised by H.-S. Philip Wong. She earned B.S. degree from Peking University in 2020. She received 2024 IEEE EDS PhD Fellowship and 2024 IEEE IEDM Best Student Paper Award.
URL:https://www.quantumx.washington.edu/calendar/uw-ece-research-colloquium-lecture-series-shuhan-liu-stanford-university/
LOCATION:Electrical and Computer Engineering (ECE)\, Room 037\, 185 W Stevens Wy NE\, Seattke\, Washington\, 98185
CATEGORIES:Electrical & Computer Engineering
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DTSTART;TZID=America/Los_Angeles:20260306T133000
DTEND;TZID=America/Los_Angeles:20260306T143000
DTSTAMP:20260428T015515
CREATED:20251230T225622Z
LAST-MODIFIED:20260407T182845Z
UID:8279-1772803800-1772807400@www.quantumx.washington.edu
SUMMARY:Maxwell Parsons (University of Washington)\, QISE Seminar: Engineering Qubit Control for Scalable Quantum Systems
DESCRIPTION:Abstract \n\n\n\nQuantum computing is advancing along two primary scaling paradigms: distributed quantum systems connected through entanglement networks\, and increasingly large individual quantum processors. Both approaches require not only long-lived qubits\, but control architectures deliberately engineered to support error correction at scale. In my laboratory\, we investigate these paradigms through complementary experimental platforms: color-center quantum memories for networked architectures and reconfigurable neutral-atom arrays for large-scale processors. \n\n\n\nIn color-center systems\, an optically-addressable central electronic spin coherently couples to nearby nuclear spins to form a modular quantum memory with a photonic interface\, suitable for quantum networking. Here\, dominant limitations arise from structured environmental spin-noise and the common fluctuator associated with optical transitions of the electronic state. We are developing control strategies tailored to this noise environment\, engineering microwave and optical protocols that stabilize multi-spin registers and extend usable memory lifetimes in a manner compatible with networked error-correction schemes. \n\n\n\nIn neutral-atom systems\, we explore opportunities enabled by three-dimensional qubit geometries uniquely accessible in optically trapped atom arrays. Three-dimensional connectivity offers architectural advantages for efficient error correction\, but imposes stringent requirements on local optical control and crosstalk suppression. At the same time\, three-dimensional geometries can enable scaling in physical qubit number due to the re-use of optical power across layers of qubits for trapping and gate control.  We are co-designing 3D neutral-atom architectures and scalable optical control hardware to match qubit geometry to fault-tolerant operation and are establishing a dedicated testbed for developing and characterizing these strategies. \n\n\n\nAcross both efforts\, the central theme is control–architecture co-design: engineering qubit control systems that are intentionally matched to geometry\, noise environment\, and error-correction strategy. \n\n\n\nBio \n\n\n\nMax Parsons is an Assistant Professor in the Department of Electrical & Computer Engineering. His research focuses on advancing quantum hardware for computing\, sensing\, and communication by developing scalable control of neutral atoms and solid-state quantum systems. At UW\, he leads efforts in optical control of qubits and experimental testbeds for neutral atom quantum processors and spin-defect quantum memories.  Parsons completed his PhD in Physics at Harvard University in 2016\, where he pioneered techniques for laser cooling and atom-resolved imaging of fermionic atoms for quantum simulation. Prior to joining UW in 2022 to develop the QT3 lab\, he worked in industry on mixed-reality displays at Meta’s Reality Labs and on neutral-atom quantum computing hardware at Atom Computing. He is an inventor on more than 35 patents in quantum computing and mixed-reality technologies.
URL:https://www.quantumx.washington.edu/calendar/maxwell-parsons-university-of-washington/
LOCATION:Electrical and Computer Engineering (ECE)\, Room 037\, 185 W Stevens Wy NE\, Seattke\, Washington\, 98185
CATEGORIES:Electrical & Computer Engineering
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