Friday, May 7, 11:00am PT
In recent years, QC hardware has progressed considerably with small systems being prototyped by industry and academic vendors. However, there is a huge gap between the resource requirements of promising applications and the hardware that is buildable now; qubit counts and operational noise constraints of applications exceed hardware capabilities by 5-6 orders of magnitude. Our work seeks to enable practical QC by bridging this gap: from the top with novel compiler techniques and algorithmic optimizations to reduce application requirements and from the bottom via system architectures efficiently exploiting scarce QC resources.
Margaret Martonosi is the H.T. Adams Professor of Computer Science at Princeton University and currently leads the Directorate for Computer and Information Science and Engineering (CISE) at the US National Science Foundation. Her research focuses on computer architecture and hardware-software interface issues in both classical and quantum computing systems. She is an elected member of the National Academy of Engineering and the American Academy of Arts and Sciences, and she is a Fellow of the ACM and IEEE.
Prakash Murali is a final year Computer Science Ph.D. student at Princeton University. His research interests include architecture and compilation for quantum computers, and his recent work includes the development of noise adaptive compilation techniques that optimize programs based on the noise characteristics of near-term devices, and architectural design techniques for improving the reliability of trapped-ion systems. He is an IBM Ph.D. Fellowship recipient and an IEEE Micro Top Pick award winner.
In this talk, we present two cross-cutting optimizations that narrow the applications-to-hardware resource gap. First, we present noise-adaptive compilation techniques that optimize applications for the spatio-temporal noise variations seen in real QC systems. Using real executions, we demonstrate average fidelity improvements of 3X using noise-adaptivity, compared to industry compiler tools. Second, on the architecture front, we study instruction set design issues considering application requirements and hardware gate calibration overheads. Current QC systems either use ISAs with a single two-qubit gate type or families of continuous gate sets. Using realistic architectural simulations based on Google and Rigetti hardware, we show that QC instruction sets with 4-8 two-qubit gate types are best suited for expressing application requirements, with tractable calibration overheads. In response to our work, several industry vendors have included noise-adaptivity and its extensions as part of their toolflows and adjusted device architecture to expose more native operations and hardware characterization data.
Hosted by the Northwest Quantum Nexus (NQN), a coalition led by the U.S. Department of Energy’s Pacific Northwest National Laboratory, Microsoft Quantum, and the University of Washington. These web-based seminars feature experts on quantum computing and its applications, and support NQN’s goal of creating a vibrant industry that will contribute to the economic vitality of the region. For questions, contact email@example.com